1. Field of the Invention
The invention relates generally to a static random access memory (SRAM) and, more particularly, to an SRAM with a reduced number of wires for write circuitry in the SRAM.
2. Description of the Related Art
Static random access memories (SRAMs), in general, and high-performance domino SRAMs, in particular, are well known in the art. An SRAM device generally has an array of SRAM cells coupled to true and complement bitlines as well as wordlines. When a wordline is asserted, SRAM cells coupled to the asserted wordline are ready for either a read or write operation. When a wordline is deasserted, SRAM cells coupled to the deasserted wordline are holding the data bits stored in the cells in a previous clock cycle.
Typically, a conventional SRAM device has a plurality of write circuits and a plurality of write predriver circuits for writing write data input to a selected number of SRAM cells in the SRAM device. A write predriver circuit generally receives the write enable signal and write data input. The write predriver circuit is also coupled to a corresponding write circuit to activate or deactivate the write circuit depending on the values of the write enable signal and write data input.
In a prior art SRAM configuration having split local and continuous bitlines, the write data input is combined with the write enable signal to create a local write signal that runs down a one-dimensional array (i.e., a column) of SRAM cells in parallel with the bitlines. This necessitates a wire for a local write signal for every one-dimensional array of SRAM cells in parallel with the bitlines.
Therefore, a need exists for an SRAM device with a reduced number of such wires required for carrying local write signals to the write circuits.
The present invention provides an improved memory device with a reduced number of wires for carrying local write signals to write circuits of the memory device.
The memory device includes an array of memory cells. A plurality of local true bitlines is coupled to the array of memory cells. A plurality of continuous complement bitlines is coupled to the array of memory cells. The memory device also includes a plurality of write circuits. At least one write circuit is coupled to at least one continuous complement bitline and at least one local true bitline. Thus, at least one write circuit receives information on a data input from the continuous complement bitline and controls the local true bitline. At least one local write line is coupled to at least two of the write circuits for providing a write enable signal to the two write circuits.